1. Field of the Invention
The present invention relates to memory access control logic circuits. More particularly, the present invention relates to a novel multi-mode controller for accessing a plurality for different types of commercially available dynamic random access memory chips (DRAM) which form a main storage unit (MSU) of a computer.
2. Description of the Prior Art
Main storage units (MSUs) are typically used with main frame computers. More recently, powerful micro processor chips of the type made by Intel and Motorola have been incorporated into small powerful computing systems which incorporate therein large amounts of dynamic random access memory (DRAM) storage. The trend toward faster computing speeds and the use of reduced instruction set chips (RISC) in workstations of the type used for graphics, simulation and various computer-aided design (CAD), computer-aided engineering (CAE) and computer aided manufacturing (CAM), have imposed a need for faster active memory chips and larger sizes of the memory storage.
One way to increase the speed of DRAM memory chips is to reduce the size of the discreet devices on the chips and/or to place more memory cells on the same chip or real estate. Another way of accomplishing faster memory access is to employ a chip that is inherently faster by virtue of its design and logic families such as ECL technology versus TTL technology and also the type of memory such as page mode verses static column mode designs.
When designing a computer for use with memory boards or MSUs, it would be desirable to work with DRAM memory chips of the latest and fastest commercially available design that is also cost efficient, thus, the mainframe computer should be capable of accepting different size memory chips as well as different types of memory chips.